I2C Tutorial

What is I2C?

        I2C (Inter-Integrated circuit), invented by Philips semiconductor in 1982. I2C is mainly use to connect system control devices such temperature sensors, voltage monitors, this bus mainly take cares of the system health.

Why I2C? do we have any other bus for this purpose?

        Yes, we have SPI (serial peripheral bus), for this purpose, but compare to I2C, SPI has few draw backs so i2c is the better option to choose.

What are the drawbacks with SPI compare to I2C?

·         I2C uses two pins to communicate (SDA, SCL).

·         SPI needs four pins (MOSI, MISO, SS, CLK) to communicate, if the slave devices are more then we need extra pins (SS)

·         I2C supports multi masters, SPI doesn’t

Does i2c synchronous or asynchronous?

        I2C is synchronous bus, since it uses clock line to communicate. Serial ports are asynchronous, because it sends all the bits at a time without waiting.

What is the I2C speed?

·       100 Khz

·       400 Khz

·       3Mhz

        We can configure the i2c bus speed by configuring the FDR(Frequency divide register) from processor.

Basic I2C communication protocol?

        When the master (your controller) wishes to talk to a slave it begins by issuing a start sequence on the I2C bus. A start sequence is one of two special sequences defined for the I2C bus, the other being the stop sequence. The start sequence and stop sequence are special in that these are the only places where the SDA (data line) is allowed to change while the SCL (clock line) is high. When data is being transferred, SDA must remain stable and not change whilst SCL is high. The start and stop sequences mark the beginning and end of a transaction with the slave device.

All I2C addresses are either 7 bits or 10 bits. The use of 10 bit addresses is rare and is not covered here. All of our modules and the common chips you will use will have 7 bit addresses. This means that you can have up to 128 devices on the I2C bus, since a 7bit number can be from 0 to 127. When sending out the 7 bit address, we still always send 8 bits. The extra bit is used to inform the slave if the master is  writing to it or reading from it. If the bit is zero the master is writing to the slave. If the bit is 1 the master is reading from the slave. The 7 bit address is placed in the upper 7 bits of the byte and the Read/Write (R/W) bit is in the LSB (Least Significant Bit).

The placement of the 7 bit address in the upper 7 bits of the byte is a source of confusion for the newcomer. It means that to write to address 21, you must actually send out 42 which is 21 moved over by 1 bit.

1.Send a start sequence
2.Send the I2C address of the slave with the R/W bit low (even address)
3.Send the internal register number you want to write to
4.Send the data byte
5.Send the stop sequence.

As an example, address of 0xE0. you would write 0x51 to the command register at 0x00 like this:
1. Send a start sequence
2. Send 0xE0 ( I2C address of the SRF08 with the R/W bit low (even address)
3. Send 0x00 (Internal address of the command register)
4. Send 0x51 (The command to start the SRF08 ranging)
5. Send the stop sequence.

Read from Device.

1. Send a start sequence
2. Send 0xC0 ( I2C address of the CMPS03 with the R/W bit low (even address)
3. Send 0x01 (Internal address of the bearing register)
4. Send a start sequence again (repeated start)
5. Send 0xC1 ( I2C address of the CMPS03 with the R/W bit high (odd address)
6. Read data byte from CMPS03
7. Send the stop sequence.

Memory mapped i/o VS Port mapped i/o

                                    

                                      In memory-mapped systems, the I/O device is accessed like it is a part of the memory. Load and Store commands are executed for reading from and writing to I/O devices, just like they are used for the memory (port-mapped has special commands for I/O). This means I/O devices use the same address bus as memory, meaning that CPU can refer to memory or the I/O device based on the value of the address. This approach requires isolation in the address space: that is, addresses reserved for I/O should not be available to physical memory.

Below is an image of a simple, basic computer system. The case is much more complicated in contemporary systems.

Port-Mapped I/O

According to Wikipedia

Port-mapped I/O often uses a special class of CPU instructions specifically for performing I/O. This is found on Intel microprocessors, with the IN and OUT instructions. These instructions can read and write one to four bytes (outb, outw, outl) to an I/O device. I/O devices have a separate address space from general memory, either accomplished by an extra "I/O" pin on the CPU's physical interface, or an entire bus dedicated to I/O. Because the address space for I/O is isolated from that for main memory, this is sometimes referred to as isolated I/O.

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As for the advantages and disadvantages: since the peripheral devices are slower than the memory, sharing data and address buses may slow the memory access. On the other hand, by the I/O simplicity memory-mapped systems provide, CPU requires less internal logic and this helps for faster, cheaper, less power consuming CPUs to be implemented. The logic is similar to that of RISC systems: reduce the complexity, get a more dedicated and a robust system which comes quite handy for embedded systems, for example.

On the contrary (again from Wiki):

Port-mapped I/O instructions are often very limited, often providing only for simple load and store operations between CPU registers and I/O ports, so that, for example, to add a constant to a port-mapped device register would require three instructions: read the port to a CPU register, add the constant to the CPU register, and write the result back to the port.

I strongly recommend that you read that wiki article for further information.

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To answer one of your questions:

What or where am I writing to if it's not in memory?

You are writing to the registers of the I/O interface through the data bus, which later (when ready) sends the data to the actual I/O device. Below is an image of an example I/O device interface.